ÿþ<HEAD><TITLE>September/October 1998: ºó¼Ì³ß´ç£¬µ±´úÃÜ·â¼¼Êõ</TITLE> <META content="Based in Silicon Valley, California, Tru-Si Technologies is the world leader in manufacturing its proprietary Atmospheric Downstream Plasma (ADP) equipment for semiconductor wafer processing applications." name=description> <META content="Processing Equipment, flat panel display, cleaning equipment, dry etch systems, photoresist application, stripping systems," name=keywords> <META content="Tru-Si Technologies" name=Name> <META content="text/html; charset=windows-1251" http-equiv=Content-Type><LINK href="trusi.css" rel=stylesheet title=style type=text/css></HEAD> <BODY><BR> <H2>The Next Dimension, Advanced Packaging</H2> <CENTER> <TABLE border=0 width="95%"> <TBODY> <TR> <TD> <H3>Publication: Advanced Packaging "! Magazine</H3> <H4>Thinner packages vital for third-dimensional expansion</H4>. <P><B>By</B> Sergey Savastiouk, Oleg Siniaguine and Mark DiOrio <P>Moore's Law originally stated that the number of components on a chip or the component density would double every 12 months. As this task became more difficult, Moore corrected the doubling period to 18 to 24 months in the mid-1970s, and it may become even longer in the future. It is clear that integrated circuit (IC) packaging continues to be driven to miniaturization, not only in footprint (area of board space used), but also in package thickness or height. Reducing package thickness requires creating a thinner wafer or chip (die), which leads to considering a third-dimension to apply Moore's Law to circuit density per unit volume. <BR><BR> <P> <CENTER><IMG height=171 src="articlesbp1.gif" width=277> <BR><FONT size=1>Figure 1. Interation of wafer thickness, wafer diameter and die thickness. The industry has decreased chip thickness nearly five percent per year since wafer thinning became a requirement.</FONT></CENTER> <P>A thinner chip or die provides for many benefits such as requiring less space, improved thermal perform mce, better power dissipation and higher reliability. Such performance factors are essential to our ability to continue following semiconductor industry road maps. This article examines the need for thinner packages, the performance benefits of thinner die, and the options that are available to produce thinner die and wafers. It also introduces a modified concept of Moore's Law, expanding it to the third-dimension, based on the analysis of trends in advanced packaging. <H4>Packaging Trends</H4>In IC packaging, the adage "smaller is better" is closely coupled with "thinner is better." Early through-hole package types such as dual in-line packages (DIP) had package thickness dimensions of 150 mil (4 mm). As we migrated to the smaller footprint surface mount components such as small-outline integrated circuits (SOIC), the package thickness dimension was reduced to the 50 to 90 mil (1.2 to 2.5 mm) range. This package thickness dimension was then driven down to about 20 mil (0.85 mm) for applications such as smart card modules and micro ball grid arrays (µBGA). As we continue to evolve our efforts, today's chip scale packaging (CSP) packages approach 10 mil (0.4 mm). <BR><BR> <H4>Die Thickness and Wafer Diameter Trends </H4>In the early generation of through-hole packages, (i.e., DIPs), chips from 4 to 6" diameter wafers were typically 21 mil thick, and very little wafer thinning was required. More recently, surface mount devices required die thickness of 10 to 12 mil and are mostly processed on 6 (150 mm) and 8" (200 mm) diameter wafers. <BR><BR>Wafer thinning allowed the manufacture of thin surface mount packages, including the leadframe thickness, dieattach epoxy thickness and wire loop height. Demands for wafer thinning will be even greater as we go to 12" (300 mm) wafer diameter while being faced with the requirement to reduce package thickness for the next generation of components (Figure 1). This trend is expected to continue, enabling the industry to keep doubling component density (expressed on a unit volume basis). <BR><BR> <H4>Performance Benefits of Thin Die</H4>As electronics applications shrink in size, IC packaged devices must be reduced in footprint and thickness. By reducing package thickness, the primary consideration is the die thickness, which has other important performance benefits. <BR><BR> <H4>Space Requirements</H4>Thinner packages are the main motivation for packaging and assembly to migrate to thinner die. Certain applications require very thin packages: memory cards; PCMCIA cards; smart cards; some small disk drives; cellular telephones; portable computing; and consumer electronic items. Thinning is required not only to improve silicon performance but also to meet thinner packaging requirements. <BR><BR> <H4>Power Dissipation</H4>There are performance benefits to thin die that extend beyond package miniaturization. Such benefits can be categorized as device performance and reliability enhancements. Thin die, for example, enables high performance devices to dissipate more heat. This is a critical asset as device densities continue to increase. Thinning the die reduces the serial resistance between the active circuitry and the backside of the chip, which can be in contact with a heat sink. <BR><BR> <H4>Thermal Resistance</H4>The thermal resistance of a solid material can be defined by the following equation. Essentially, it is the material thickness divided by the product of the thermal conductivity and the heat flow cross section area. <BR><BR> <H4>E = t/(k x A)</H4> <H4>where</H4> <UL> <LI>E is the conductive thermal resistance (°C/W); <LI>t is the thickness or distance through which heat must travel (m); <LI>k is the thermal conductivity (W/(m K)); <LI>A is the cross sectional heat flow area (m<SUP>2</SUP>). </LI></UL>A lower thermal conductivity with a small thickness can produce a lower thermal resistance than a higher conductivity material with a greater thickness. <BR><BR>Thermal resistance of a silicon die with the area 10x10 mm and a thermal conductivity of 145 W/m K is 0.025°C/W for the thickness 14 mil, and is reduced to 0.0035°C/W for the thickness 2 mil. If a die-attach material such as 8020 gold tin with a thermal conductivity of 57 W/m K and thickness of 1 mil is used, the combined thermal resistance is reduced correspondingly from 0.03°C/W to 0.008°C/W. <BR><BR> <H4>Device Reliability</H4>Thin die minimizes the stress on the device circuitry due to coefficient of thermal expansion (CE) within the packaged device. This is particularly true in die cracking problems exhibited in power devices. <BR><BR>With a CTE of Si of approximately 4 x 10-6/°C and a CTE of a Cu alloy lead frame material of approximately 16 x 10-6/°C, a significant amount of silicon flexure will occur. <BR><BR>Reducing the die thickness dramatically reduces stress in the die, allowing more flexibility, and reducing the chance of Si fracture (as a result of the CTE mismatch). <BR><BR> <H4>Device Electrical Performance</H4>Backside silicon damage, as a result of stress induced from the background wafer thinning operation, can have adverse effects on the electrical performance of certain device types. Damage to the silicon lattice, as a result of severe stress, can produce noise in certain device types such as precision power amplifiers. In similar device types, such as op amps, inconsistent or high stress fields can adversely affect off-set voltage and current performance, thereby reducing yield and downgrading parts. <BR><BR> <H4>Stacks</H4>Die must be thinned for use in vertical memory stacks. It is desirable to fit chip stacks inside standard packages (this requires thin die). For example, Sharp Corp. is mass-producing its first devices, based on its stacked CSP technology. Die and wafers must be thinned if the application requires stacking of the die/wafers in construction of a micro electromechanical microwave systems (MEMS) product. Pressure sensors can be made by physically bonding one layer of silicon with the sensor to another layer of silicon containing a cavity to yet another silicon device which contains the active circuitry. A number of MEMS applications require thinning of the silicon material. <BR><BR> <H4>Reduction of Saw Street Dimension </H4>As the number of chips per wafer is increased, the dimensions associated with chip layout are continually reviewed. One such dimension is the saw street dimension, or the area between the die that has been allocated for sawing or dicing. Currently, the industry standard for saw street width is 4 mil. Therefore, every chip has about 2 mil width of unused Si surrounding it. As the wafer thickness is reduced from 21 to 10 mil, the potential exists to reduce the street width by as much as 50 percent with minimal effect to the sawing or dicing process. Such a reduction in saw street dimension allows for more chips per wafer. <BR><BR> <H4>Options Available to Thin Wafer and Die </H4> <H4>Four different methods are available for reducing wafer thickness: </H4> <OL> <LI>mechanical surface grinding <LI>chemical mechanical polishing (CMP) <LI>wet etching <LI>atmospheric downstream plasma etching (ADP). </LI></OL>While CMP and wet etching are used primarily in the wafer manufacturing and device fabrication areas, these techniques are known for their ability to reduce stress in wafers and planarize the device surface, not their ability to thin wafers. <BR><BR>Mechanical surface grinding is the most commonly used process to thin wafers after processing; however, it does induce significant stress and damage into the silicon wafer. Grinding has the capability to reduce bulk wafer thickness at a significant rate, thereby making it a very affordable process. Today backside grinders are installed both in the wafer fab and in some assembly areas. <BR><BR>ADP etching is an emerging technology that combines the thinning capabilities of grinding with the stress removal capabilities of CMP or wet etching. Tables 1, 2 and 3 are a comparison of the various wafer thinning options. <BR><BR>While ADP has a significantly higher silicon removal rate compared to CMP or wet etching, it does not offer the same throughput as grinding. However, the combined benefits of stress removal and wafer thinning using ADP create a technology shift. The benefits of reducing residual stress in processed wafers are immense and far reaching. Some advantages include: <BR><BR> <UL> <LI>damage (stress) free crystal structures enhance operating frequencies and decrease noise of the device <LI>uniform stress fields maintain matched characteristics of embedded devices <LI>thin, stress free die provide a lower VCE<SUB>(sat)</SUB> in discrete devices <LI>improved backside morphology improves thermal and electrical characteristics of the device. </LI></UL> <H4>Additional Benefits of ADP</H4>Studies indicate that ADP has the potential to reduce 8" wafers to 2 mil thickness, while maintaining a total thickness variation (TTV) of 2 percent or less. The ADP process is contactless and does not require protective tape to be applied to the top side of the wafer. Eliminating protective tape significantly reduces processing costs and allows the ability to process inked wafers. The ability to process inked wafers clearly separates ADP from all other wafer thinning processes (Figure 2). <BR><BR>ADP is the only wafer thinning process that has the potential to handle individual chips (die after sawing). The current ADP source can be used to process individual die, instead of wafers. Because the process is contactless, no protection is required for the chip. As an additional benefit, edge chips are removed and sharp edges are rounded in the process (Figure 3). <BR><BR> <H4>Difficulties in Thin Die Handling</H4>Thinner wafers are more fragile and prone to handling damage, especially for larger diameter wafers. Wafer breakage due to handling can be as high as 20 percent on a 10 mil thick, 200 mm diameter wafer. Reducing a 200 mm wafer from 21 to 10 mil in thickness reduces the wafer's structural strength by more than 50 percent. <BR><BR>Because it has become increasingly difficult to ship and handle 10 mil thick 8" wafers that have been ground from 21 mil, some device manufacturers are shifting wafer back grinding from the fab area to the assembly location. <BR><BR>Not only are thinned wafers fragile because of their dimensions, but they are also weakened by residual stress and damage caused by the back grinding process. <BR><BR> <H4>Dicing or Wafer Sawing</H4> <P> <CENTER><IMG height=113 src="articlesbp2.gif" width=216> <BR><FONT size=1>Figure 3. Transition electron microscopy cross section shows die after micro-grinding (top) and after ADP etching (bottom).</FONT></CENTER>While sawing a 10 mil wafer is easier than sawing a 21 mil wafer, the preceding back grinding process can induce an extreme amount of stress into the silicon wafer. Therefore, care must be taken to prevent excessive chipping of either the top or back side of the chip. Excessive topside chipping can result in damage to the IC's active circuitry causing device failure or performance degradation. To avoid excessive topside chipping, the feed rate of the saw must be slowed considerably. <BR><BR>Backside chipping can be equally important to device failure and performance because it can cause stress cracking in devices that have undergone thermal or power cycling, which can have adverse effects on die shear strength, die strength and device reliability. Furthermore, with flip chip assembly, the back side of the chip is more visible and increases backside chipping. <BR><BR> <H4>Die Bonding</H4>A certain degree of care must be exercised in the die bonding operation when processing thin wafers. The timing of the plunge up and pick up sequence steps must be closely timed to avoid silicon damage to the backside by the plunge up needle (which has been proven to cause stress risers that lead to chip cracking and device failure) or mechanism. <BR><BR> <H4>Conclusion</H4>Performance benefits to thin die far outweigh the difficulties. Thin die enables thinner packages with improved device performance characteristics. Furthermore, device performance can be improved through reductions in stress caused by wafer thinning. <BR><BR>The emerging technology of ADP holds great opportunity for packaging because it provides the capability to reduce wafer thickness in a stress free manner, and it is the only technology that can be applied at both the wafer and the individual die level. (This holds significant merit and opportunity for the advancement of packaging and assembly.) Device types receiving the most benefit from ADP processing include linear/analog/mixed signal, power, radio frequency, digital bipolar and discrete. <BR><BR>We can also adjust Moore's Law to add the third-dimension of die thickness to achieve higher component packing density per unit volume. Companies understand the need to keep up with Moore's Law or else fall behind the only choice is to open the next dimension in the company's development. <BR><BR> <H4>References</H4> <OL> <LI>Savastiouk, Siniaguine, Hammond, Atmospheric Downstream Plasma - A New Tool for Semiconductor Processing, Solid State Technology, July 1998. <LI>Savastiouk, Siniaguine, Hammond, Atmospheric Downstream Plasma, European Semiconductor, June 1 998. <LI>Weiss, Dean, DiOrio, Wafer Di&amp;ng...Step by Step, Advanced Packaging Magazine, January 1998. <LI>DiOrio, Wafer Backgrinding - The Back-End of Fab or the Front-End of Assembly?, Advanced Packaging Magazine, February 1998. <LI>Pinamaneni, DiOrio, Material/ Effects on the Performance and Reliability of High Power Mo/ded Dua/-inLine Packages, IEEE 38th Electronics Components Conference Proceedings, 1988. <LI>Pinamaneni, DiOno, Assembly Techniques Related to Die Crack in High Power Dissipation MDlPs, IEEE 38th Electronics Components Conference Proceedings, 1988. </LI></OL></TD></TR></TBODY></TABLE></CENTER> <HR SIZE=2 width="80%"> <CENTER><B>Tru-Si Technologies</B><BR>657 N. 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