ÿþ<HEAD><TITLE>June, 1998: Atmospheric downstream plasma, European Semiconductor</TITLE> <META content="Based in Silicon Valley, California, Tru-Si Technologies is the world leader in manufacturing its proprietary Atmospheric Downstream Plasma (ADP) equipment for semiconductor wafer processing applications." name=description> <META content="Processing Equipment, flat panel display, cleaning equipment, dry etch systems, photoresist application, stripping systems," name=keywords> <META content="Tru-Si Technologies" name=Name> <META content="text/html; charset=windows-1251" http-equiv=Content-Type><LINK href="trusi.css" rel=stylesheet title=style type=text/css></HEAD> <BODY><BR> <H2>Atmospheric downstream plasma, European Semiconductor</H2> <CENTER> <TABLE border=0 width="95%"> <TBODY> <TR> <TD> <H3>Publication: European Semiconductor</H3><B>Eliminating vacuum pumps and chambers drops the cost of a new high-etch rate, all-dry plasma source, which is complimented by a new non-contact wafer holder.</B> The drive to portable electronic devices, smart cards, multi-chip modules, PCMCIA cards, etc, forces industry to develop thinner packages and thinner chips. Simultaneously, the drive to bigger chips and lower cost-per-function forces wafers to larger diameters. To survive the processing environment, wafers must be thicker. The discrepancy between wafer thickness and chip thickness resulted in the backgrinding industry.<BR><BR>Backgrinding was originally used to create controlled surfaces for die attach. In the late 1970s, packaging began to require chips that were thinner than standard wafers and backgrinding was used to thin wafers prior to dicing.<BR><BR>Early backgrinding techniques were crude. Even though the finished wafers (and resulting chips) were relatively thick, residual stress caused wafer bow and warp, and led to yield loss.<BR><BR>As thinner wafers were required, backgrinding techniques improved by incorporating in-feed grinding, with a second fine-grinding stage that reduced residual backside damage and stress.<BR><BR>Wet etching was introduced to remove post-grind residual damage and stress and to further thin wafers after backgrinding. But as with other semiconductor etch processes, wet etching is now being challenged by new dry etch technology.<BR><BR> <H4>RESIDUAL DAMAGE AND STRESS</H4>The depth of the residual damage and stress is a function of grinding force and grit size. Even fine grinding leaves residual damage and stress and productivity is greatly reduced by using lighter grinding and finer grit size.<BR><BR>Backside damage can be divided into two layers: (1) A damaged layer at the surface that contains microcracks, and (2) a deeper layer containing only crystal dislocations.<BR><BR>Both layers contribute to warpage and a lowering of the fracture strength of the wafer.<BR><BR>The significance of the warpage and weakening of the wafer is a function of wafer diameter and thickness. For wafers 100-150 mm in diameter, current backgrinding techniques are satisfactory in production of wafers thinned to about 250 µm.<BR><BR>Both packaging technology and chip density are driving wafer thicknesses below 250 µm. Leading-edge package designs require thinner chips for thin package profiles and to improve thermal dissipation. Thinner wafers allow device manufacturers to increase the number of die per wafer. Since thinner wafers are sawed by thinner blades, the saw street width can be reduced, leaving more area available for device patterns. But thinner wafers pose handling risks:<BR><BR>As wafer diameters increase, so does sensitivity to handling. Residual damage and stress must be eliminated to produce thinned wafers 200 mm and 300 mm in diameter with sufficient strength to survive subsequent kindling and dicing operations. Even more important, the integrity of thinned chips is threatened by the presence of microcracks that can propagate during assembly or even after the chip has been packaged.<BR><BR>The trend to thinner wafers and thinner chips (Figure 1) is forecast to continue down to 100-150 µm and even less. Wafer strength requirements of large diameter wafers limit backgrinding to thicknesses of 200-250 µm, so new technology is required.<BR><BR> <H4>WET VS DRY ETCHING</H4>The current technique for removing backside damage/stress is wet etching. Improvements in wafer strength of 2-lOx have been demonstrated by removing 25-100 µm of silicon from background wafers. Removing 25 µm is reported to restore mechanical strength of background wafers, regardless of grinder type. With more refined backgrinding, depth of residual damage is less, and Iess removal is required.<BR><BR>Wet etching can also be used for thinning wafers. Performance drawbacks are lower productivity due to the longer required dwell time and difficulties in maintaining uniform wafer thickness when a large amount of material is removed.<BR><BR>Wet etching was used as a first step for many applications, but was often ultimately supplanted by dry etching. Driving forces are the need to control the process, eliminate complex hazardous waste disposal systems, avoid transportation of wet chemicals, reduce worker protection requirements, etc.<BR><BR>The benefits of this transition to dry etching, in addition to superior process results on the wafer, have been: better uniformity, better control of reaction kinetics, safer materials handling, and less complex hazardous waste disposal.<BR><BR>The footprint of wet etching systems may be relatively small; however door space requirements are substantial when all the hazardous materials-handling subsystems are taken into account.<BR><BR> <H4>NEW PLASMA SOURCE</H4>Typical all-dry etching systems used in wafer fabrication operate in vacuum and do not offer the removal rates necessary for economic dry removal of wafer backside damage and stress.<BR><BR>A new plasma source - Atmospheric Downstream Plasma (ADP) - has been developed operating at atmospheric pressure and provides etch rates at least two orders of magnitude higher than plasma systems operating in vacuum (Table 1). Eliminating vacuum pumps and vacuum chambers, the new source also greatly reduces the cost associated with all-dry wafer processing.<BR><BR>The design of the ADP source allows it to readily accept reaction gases into the plasma region where they are 100% decomposed and available for reaction in the chemical reaction zone downstream from the plasma region. Because the plasma operates at atmospheric pressure, charged species quickly recombine outside the plasma region, dielectric surfaces are not charged, and all species achieve a relatively low average kinetic energy in the chemical reaction zone.<BR><BR> <H4>NEW WAFER HOLDER</H4>Grinder-related side effects on wafer shaping can include large shape changes, non-uniform thickness removal and added roughness. In addition, stress caused by protective tape can cause wafer warpage. To avoid problems of handling thinned wafers without harming the integrated circuitry on the wafer frontside, a new, non-contact handling system has been developed.<BR><BR>The NoTouch wafer holder helps meet more stringent handling needs by creating a lifting force using a modified Bernoulli principle, in which a flow of gas over the wafer surface prevents contact. In this new design, the holding gas moves downward through miniature vortices to create additional lifting force. Distributing several vortices over the wafer produces a gentle, uniform force.<BR><BR>Even edge contact is avoided because the wafer is lifted into a recess, and the gas supplying the Bernoulli force exits at the wafer edge, centring the wafer. Exiting gas also prevents etch gases at the wafer backside from reaching the wafer front circuitry. Frontside tape protection is therefore not required for either wafer thinning or for backside damage and stress removal. Moreover, the holder does not constrain the wafer so it does not add any additional stress.<BR><BR>ALL-DRY WAFER BACKSIDE TREATMENT SYSTEM This new plasma source has been incorporated into the Tru-Etch series of wafer backside treatment systems that provide high reaction rates for economic removal of wafer backside damage and stress and for wafer thinning. The system series handles wafers of 100, 150, 200 and 300 mm in diameter using the NoTouch wafer handling system. <BR><BR>The systems use the ADP source to remove silicon by the well-known reaction of silicon with oxygen and a fluorine-containing plasma. Because the vigorous plasma source in the Tru-Etch 2000 system reacts 100% of the fluorine-bearing gases, hazardous waste is minimized and the exhaust is readily treated by a water-based gas scrubber. <BR><BR>In the process chamber, multiple wafers are loaded onto a process carousel and rotated over the plasma source. Repeated exposures with programmed motion assure uniform removal and prevent over-heating. Uniformity of 1% has been demonstrated.<BR><BR>Four cassette nests are provided to eliminate the need to have an operator waiting to exchange cassettes. The wafer handling system is designed so the process chamber is essentially in continuous production. <BR><BR>PROCESS INTEGRATION Automated backgrinding systems typically operate on a cassette-to-cassette basis. After a post-grind clean (within the grinding system or external to it), the same cassette of wafers can be placed in a Tru-Etch series reactor for backside damage and stress removal without any other processing On exiting the system, the wafers will be free of backside deposits, damage, stress and microcracks. <BR><BR>Throughput depends on wafer diameter and amount of material to be removed. For 200 mm wafers and a damage/stress removal process for 5-10&amp;#181m, throughput will exceed 100 wafers per hour (much higher for smaller wafers). Throughput for multistage backgrinding is significantly less, s a system servers several backgrinders. <BR><BR>Due to the high uniformity of the Tru-Etch removal process, device manufacturers can extend wafer thinning to thicknesses below 75 µm. To maintain high throughput, a balance between backgrinding and etching must be optimized. The best process integration will be to backgrind to a thickness and damage depth that assures high wafer survival followed by dry etching to remove damage and thin the wafers. <BR><BR>PERFORMANCE With a wafer throughput of roughly 100 200 mm wafers per hour, a Tru-Etch system adds less than 52 per processed wafer, including depreciation, utilities, consumables, floorspace allocate on and waste disposal. <BR><BR>Toul Thickness Variation (TTV) of less than 2% 6r 8" wafers has been demonstrated with removal of 20 ,&amp;#181m of silicon and 100 wafers per hour throughput. <BR><BR> <H4>Systems benefits include: </H4> <UL> <LI>Enhance overall dence yield by eliminating backside damage <LI>Provide a cosmetically smooth backside surface <LI>Eliminate subsurface damage and micro cracks that can cause irregular die edges <LI>Provide a stress-free process that does not add to wafer bow <LI>Eliminate the need for frontside wafer surface protection <LI>Require little change in process flow <LI>Operate at atmospheric pressure <LI>Provides a cost-effective solution to damage-free wafer thinning. </LI></UL>Authors: Sergey Savastiouk PhD, Oleg Siniaguine PhD, Tru-Si Technologies Inc, Sunnyvale, California and Martin L. Hamnnond PhD, TMX International , Cupertino, California<BR><BR></TD></TR></TBODY></TABLE></CENTER> <HR SIZE=2 width="80%"> <CENTER><B>Tru-Si Technologies</B><BR>657 N. Pastoria Ave. <BR>Sunnyvale, CA 94085 <BR>Phone: (408) 720-3333<BR>Fax: (408) 720-3334<BR>Email: <A href="mailto:inform@trusi.com">inform@trusi.com</A><BR><A href="http://www.trusi.com/" target=_top>Tru-Si Technologies Home Page</A><BR></CENTER><BR><BR></BODY>