ÿþ<HEAD><TITLE>Chip Scale Review article on grinding</TITLE> <META content="text/html; charset=windows-1252" http-equiv=Content-Type> <META content="Microsoft Word 97" name=Generator></HEAD> <BODY><FONT size=4> <P>ADAPTATION OF BACKGRINDING FOR THIN WAFER PRODUCTION</P></FONT><FONT face="Courier New" size=2></FONT><FONT size=2> <P>By Pat Halahan CTO Tru-Si technologies, Phil Marcoux Tru-Si Technologies, Frank Kretz, and Tony Schraub.</P></FONT> <P>INTRODUCTION </P> <P>Back grinding is the traditional method for thinning silicon wafers from their initial wafer thickness, on which semiconductor films are built, to the smaller thickness suitable for final packaging of die after dicing. Grinding is fast and produces excellent TTV (Total Thickness Variation) and surface finish. Now for an emerging market for thinner and ultra thin die, grinding is still the preferred thinning method but traditional grinding requires modifications and some additional treatment. This article discusses the current state of thin-wafer grinding and the complementary additional technologies required to address disadvantages arising in the grinding of such very thin wafers.</P> <P>For thin die applications the wafers are ground very thin (and fragile) using diamond abrasive grinding wheels on rotary grinders before being diced. <B></B>Modern grinders rotate the wafer on a vacuum chuck and feed the rotating grind wheel into the face of the wafer at a precisely controlled rate (or at a controlled force). The wheels, a critical part of grinding, are made by graded diamond abrasive embedded in specially engineered binders on the wheel edge.</P> <P>Today s production limit for grinding is around, although most thin wafer production is at around 250um. Yield in the grinding and downstream processes like de-taping have made it very difficult to go lower than 150 um, let alone below 250um. Die cracking during assembly and life test also have added to this limit.</P> <P>More recent applications and packaging techniques increasingly demand the die be thinned to below 200 microns (8 mils or 0.008") for smart cards, flash memory and some stacked die applications for portable devices so requiring "Thin Wafers". Now the same applications are driving the thinning technology to "Ultra Thin Wafers" whose final thickness is below 100 micron, some down as low as 50-micron thickness (2mils)! There are some special techniques being tried for making these ultra-thin die with limited success. Normal grinding and post processing is still preferable.</P> <P>Thin and Ultra Thin die are difficult to handle and package. The thin die is flexible and so Pick and Place has to be tuned and frame tapes may need to be changed. Other changes may need to be made to other processes to accommodate ultra thin die. One of the biggest issues is die cracking during bonding or life testing. Much analysis has been done on this die cracking and it has been found that much of it is due to the die backside damage. The damage is coming from the fact that grinding is basically a process of scratching away silicon using diamond bits. The scratching causes weaknesses in the silicon wafer, much the same way it does in a pane of glass when one is trying to cut the glass using the scribe and break technique. Thus, the removal of surface or sub-surface damage (SSD) has recently emerged, as the new technology required in thin and ultra thin die applications in production. Another requirement for thin wafer production is special handling tools and related storage and shipment carriers for these thin wafers. The third requirement is for special thin wafer grinding recipes.</P> <P>The grinding process itself usually consists of two steps: a coarse abrasive wheel grind (typically ~350-500grit diamond abrasive) which removes material rapidly, but damages the surface by gouging the silicon away; followed by a fine abrasive wheel grind which removes most of the grinding damage by a more gentle grinding with fine abrasives (2000-3000 grit) using ductile grinding technology.</P><B> <P>Figure 1</B> shows an AFM (Atomic Force Microscope) picture of the surface of a silicon wafer after 500-grit grind step.</P> <P><IMG height=327 src="Image4.jpg" width=436></P><B> <P>Figure 2</B> shows an AFM after 200 grit grind. The surface still shows considerable damage.</P> <P><IMG height=337 src="Image5.jpg" width=450></P> <P>However, some of the coarse grind damage remains even after fine grind, or this damage is driven into the silicon surface after the fine grind process. </P><B> <P>Figure 3</B>. Cross sectional view of subsurface post-grind damage.</P> <P><IMG height=326 src="Image6.jpg" width=403></P> <P>So to further remove the damage and to repair the edges, post-grind sub-surface damage removal is utilized as a third step to strengthen the wafers and die. In this way, the thin and ultra thin wafers are robust enough to be handled by special automation methods, and the wafer can be diced into die, which are strong enough for their application environment. </P> <P>Three methods are being utilized to remove grinding damage: traditional loose-abrasive polishing, wet etching, and dry plasma etching. The following table shows some of the aspects of these 3 processes.</P> <TABLE border=1 cellPadding=7 cellSpacing=1 width=590> <TBODY> <TR> <TD vAlign=top width="20%"><B> <P>Process</B></P></TD> <TD vAlign=top width="28%"><B> <P>Finish type</B></P></TD> <TD vAlign=top width="52%"><B> <P>Comment</B></P></TD></TR> <TR> <TD vAlign=top width="20%"> <P>Polish</P></TD> <TD vAlign=top width="28%"> <P>Very smooth and shinny</P></TD> <TD vAlign=top width="52%"> <P>Known to not get rid of all damage.</P></TD></TR> <TR> <TD vAlign=top width="20%"> <P>Wet etching</P></TD> <TD vAlign=top width="28%"> <P>Can be varied but not as shinny as polish</P></TD> <TD vAlign=top width="52%"> <P>Wet chemical danger but a well-known process. Will need more etching than dry type to remove damage.</P></TD></TR> <TR> <TD vAlign=top width="20%"> <P>Dry etch</P></TD> <TD vAlign=top width="28%"> <P>Varied but mostly dull looking</P></TD> <TD vAlign=top width="52%"> <P>Fairly new. Good COO and shows considerable strength improvements</P></TD></TR></TBODY></TABLE> <P>The first method, typically integrates a polishing step into the grinder itself.<B> </B>This method has the advantage of integrating the SSD removal into the grinder tool and also builds upon traditional CMP (Chemical-mechanical Polishing) technology. However, CMP has the disadvantage of low removal rates or high downforce requirements, which may damage very thin wafers and "drive" the sub-surface damage further into the surface by the polishing process. The second method uses wet etching to remove SSD. The spin-etching process provides for uniform removal, but the edge of the thin wafers are made sharper and more fragile.<B> </B>The third method uses dry plasma etching to remove SSD. This method has the advantage that the SSD is removed, the edges are improved by rounding of the sharp edge, and the surface roughness can be controlled where needed for adhesion. </P><B> <P>Figure 4</B> shows the backside surface after a dry etch process </P> <P><IMG height=327 src="Image7.jpg" width=436></P><B> <P>Figure 5 and 6</B> show SEM pictures before and after etching. Clearly this scratch type damage is removed.</P> <P><IMG height=194 src="Image8.jpg" width=253>&nbsp; <IMG height=190 src="Image9.jpg" width=243></P><B></B> <P>The grinding of wafers to below 200 microns thickness requires some special grinding process techniques. To begin with, the vertical grind forces allowable usually are restricted to lower levels than on the more robust thick wafers. Lower grinding forces produce less SSD and improved edge quality. The speeds of rotation and feed rates must be carefully chosen. And since the wafer is thin and flexible, the edges, which tend to lift off the vacuum chuck during grinding by the fluid forces of the coolant and rotation, must be restrained or the already thin and sharp wafer edge may be further thinned or chipped. Each manufacturer has proprietary methods to address these issues. </P> <P>The standard semiconductor wafer onto which devices are made has a carefully shaped and ground rounded edge shape; but when that wafer is thinned to less than half its original thickness, that rounded edge becomes razor sharp. Those sharp edges are especially vulnerable to chipping or indenting when they impact any hard surface, and from these chips, cracks are found which become critical flaws leading to wafer breakage under normal further processing of that wafer. So special considerations to deal with sharp edges are required in the process flow, especially when wafers are rotated at high speed (for example, in the common semiconductor cleaning technique of Spin-Rinse-Dry which spins the wafers at high speed.)</P><B> <P>&nbsp;</P> <P>&nbsp;</P> <P>&nbsp;</P> <P>&nbsp;</P> <P>&nbsp;</P> <P>&nbsp;</P> <P>&nbsp;</P> <P>&nbsp;</P> <P>&nbsp;</P> <P>&nbsp;</P> <P>&nbsp;</P> <P>&nbsp;</P> <P>Figure 7 and 8</B> are SEM pictures of a thick wafer and a thinned wafers edge. The wafer edge becomes sharper as the thickness decreases from around 250um thick.</P> <P><IMG height=186 src="Image10.jpg" width=245><IMG height=186 src="Image11.jpg" width=245></P> <P>Grinders however are limited as to the thickness they can grind to. As the wafer gets thinner the edges start to deteriorate. Figure 8 shows a 250 um-thick wafer. However when one grinds to say 150um thick, the edge is somewhere in the beveled section of the wafer. The resulting edge is chipped (see figure 9) and the whole wafer is easily broken. Removing edge damage becomes a major objective for the ultra-thin post grind wafer processes. The dry etch processes are in general much better at improving the edge profile due to not having to deal with protection of the front side from the wet chemicals and the surface tension of the acid etchants.</P><B> <P>Figure 9</B> shows an optical image of a 100um thick ground wafer and the resulting edge damage.</P> <P><IMG height=276 src="Image12.jpg" width=368></P> <P>The above considerations addressed by the grinder, the grind wheel and the SSD removal assist to make the wafers and die stronger and flexible. However, the resulting thin wafers required special handling techniques. Traditional robotic end effectors and wafer carriers designed for thick wafers are not suitable for thin wafer handling. Internal grind stresses and/or applied films distort wafers so that they are no longer flat (measured as bow and warp). Another effect on ultra-thin wafers is sag due to the flexibility and gravity. Thin wafers can bow one or more slots within a cassette making it hard for an end effector to locate. Pick up chucks or end effectors must have the ability to overcome the bow and warp of the wafer and hold them flat. In addition to the bow and warp problems, thin wafers are very fragile. Automated handling equipment can easily break the wafers if they are handled too roughly. </P> <P>&nbsp;</P> <P>SUMMARY</P> <P>In summary, the old and proven technique of back grinding silicon wafers to thin them after device films have been applied is adapting to the newer demands for very thin wafers. Changes in the grinding process itself have allowed grinders to get as thin as 250um and some less. Going ultra-thin requires other process steps.</P> <P>The addition of means to remove the microscopic grinding damage, and improved handling techniques are allowing back grinding to be extended to thin and ultra-thin wafer production.</P></BODY>